1. Field of the Invention
The invention relates generally to cache memories in computers and, more particularly, to a device and method for determining the address of a modified line in a cache memory and retrieving the tag address, data, and corresponding associativity to execute a copyback routine for the modified cache line.
2. Description of the Related Art
Cache memories in computers and other digital processing devices are generally known. A cache is a memory allotment provided for storage, usually temporary, of data which may or may not be later accessed or permanently stored. Cache memories serve to hold data most often requested by an associated processor in order to speed-up fetch and store times. Cache is thus fast memory, and so is often used in devices to optimize processor performance and enhance bus bandwidth.
Cache memories, in effect, serve to reduce the average memory access time of devices. By reducing that time, cache speeds processing by eliminating the need to access external memory which is usually larger and for which access times are much less. By locating the cache close to the processor and equipping the cache with desirable accessing and storing procedures, cache can significantly speed operation of a processing device. As may be anticipated, many factors impact the effectiveness of cache, for example, cache size, physical organization, cache line replacement/modification algorithms, and the behavior of any software being run which employs the cache memory.
In typical operation, the cache maintains a copy of the most recently used code or data from the main (or "external") memory. This code or data in cache is what is used by the processor in its iterative operations. Main memory, i.e., external memory, is employed for permanent (or extended) data storage and is typically not accessed directly by the processor. Because the processor operates with data from cache memory, data stored in the cache from time to time must be identical to the data stored in external memory. When the cache memory is modified in a desired manner during processor operation, the data in the external memory must be updated as well.
There are a number of known procedures and devices for determining modifications of cache memory and writing modified data to external memory. These procedures and their effectiveness are generally dependent upon cache organization and the other factors previously described with respect to cache effectiveness. Regardless of organization and other factors, however, prior procedures for determining modifications of cache and writing cache modifications to external memory have required a stepped check through each location of stored information in the cache to determine at each location whether there has been any modification of cached data. Only when a modification is found in that stepped check is the external memory updated. Because cache memory is being replaced continually during the operation of a processor, these prior procedures of stepping through every piece of information stored in the cache until a modification is found are time consuming relative to processor operations. It would, therefore, be an advantage over the prior art if new devices and procedures were developed for identifying modifications of cache and updating external memory to reflect those modifications, which devices and procedures would allow reduced cache memory operation times.
In discussion of cache memories, a number of particular terms are often used. For a better understanding of the objects and advantages of the present invention, definitions are provided here for certain of those terms as follows:
Associativity--a number which refers to the number of possible locations in the cache based on cache organization in which a specific address may be cached. It also refers to the number of tags which are read and compared concurrently.
Clean line--a cache line that is not marked as modified because it is not written to main memory in a copyback write policy. The fact that such a cache line is not marked as modified indicates that the line is not modified relative to the relevant main memory.
Copyback--a write policy in which a write-back is performed in the cache when data is modified within the cache. When cached data is modified, the cache is flushed. When flushed, the data in the line or lines of the cache then marked as modified is written (copied back) to the main memory.
Data array--a random access memory array that contains the data variables for use by a processor.
Data cache--a cache which is used for caching frequently used processor data variables.
Index--each cache line has an index associated with it that must be stored and compared against the index of the memory request. Indexes are kept as entries (one per line) in a directory that establishes the correspondence between the data in the cache and the particular fragment of main memory that is represented.
Line (or Block)--a cache line or block is a group of sequential words in cache memory associated with a tag.
Look-up--a look-up is performed when some data is pulled from the main memory and placed in the cache.
Modified line--a cache line is marked as modified when it is written in a copyback write policy. The mark indicates that the line contains the most recent version of the data.
Status Bits--a status bit is associated with each cache line and indicates the modified or unmodified status of the line.
Tag--the tag identifies the address of the data or instruction which is currently present in the cache. A cache tag is associated with each cache line and is stored in the tag array.
Tag array--a random access memory array that contains the address tags for cache data.
The present invention is a cache controller index address generator that provides an improved apparatus and method for determination of the address of a modified line in a cache memory and retrieval of the tag address, data, and corresponding associativity of that line in order to execute a copyback routine for the modified cache line. In practice, the invention provides a faster type of flush mechanism for a cache memory and allows for speeded cache memory operations. Thus, the invention is a significant improvement in the art.